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1 n quad output step-down module ? regulator with 3a per output n wide input voltage range: 4v to 20v n 2.375v to 20v with external bias n 0.6 v to 3.3v output voltage n 3a dc output current each channel n 1.5% total output voltage regulation n current mode control, fast transient response n parallelable for higher output current n output voltage tracking n internal temperature sensing diode output n external frequency synchronization n overvoltage, current and temperature protection n 9mm 15mm 1.82mm lga and 9mm 15mm 2.42mm bga packages typical application features description ultrathin quad module regulator with configurable 3a output array the lt m ? 4643 is a quad dc/dc step-down module (power module) regulator with 3a per output. outputs can be paralleled in an array for up to 12a capability. included in the package are the switching controllers, power fets, inductors and support components. operating over an input voltage range of 4v to 20v or 2.375v to 20v with an external bias supply, the LTM4643 supports an output voltage range of 0.6v to 3.3v each set by a single external resistor. its high efficiency design delivers 3a continuous output current per channel. only bulk input and output capacitors are needed. fault protection features include overvoltage, overcurrent and overtemperature protection. the LTM4643 is offered in a 9mm 15mm 1.82mm lga and 9mm 15mm 2.42mm bga packages with snpb (bga) or rohs compli - ant terminal finish. configurable output array* 3a 3a 3a 3a 6a 3a 3a 9a 3a 12a * note 4 1.5v output efficiency and power loss (each channel) applications n fpgas, gpus and asics applications n pcie and backside pcb mounting 4v to 20v input, quad 0.9v, 1v, 1.2v and 1.5v output dc/dc module regulator l , lt, ltc, ltm, linear technology, the linear logo, module, ltpowercad and polyphase are registered trademarks of analog devices, inc. all other trademarks are the property of their respective owners. 4643 ta01a v in1 svin1 run1 v in2 svin2 run2 v in3 svin3 run3 v in4 svin4 run4 sgnd LTM4643 clkin 22f 2 25v clkout temp gnd v out1 fb1 pgood1 v out2 fb2 pgood2 v out3 fb3 pgood3 v out4 fb4 pgood4 47f 4v 1.5v/3a 4v to 20v 40.2k 47f 4v 1.2v/3a 60.4k 47f 4v 1v/3a 90.9k 47f 4v 0.9v/3a 121k not all pins are shown load current (a) 0 55 efficiency (%) power loss (w) 75 80 85 95 1 4643 ta01b 70 65 60 90 0.0 0.6 0.4 0.2 1.2 1.0 0.8 1.6 1.4 3 2 0.5 1.5 2.5 v in = 5v v in = 12v LTM4643 4643fb for more information www.linear.com/LTM4643
2 absolute maximum ratings v in , sv in (per channel) .............................. C 0. 3v to 22v v out (per channel) (note 3) ............ C 0.3 v to sv in or 6v run (per channel) ..................................... C 0. 3v to 22v intv cc (per channel) ............................... C 0. 3v to 3.6v pgood, mode, track/ss, fb (per channel) ................................... C 0. 3v to intv cc clkout (note 3), clkin ....................... C 0.3 v to intv cc internal operating temperature range (notes 2, 5) ............................................ C 40 c to 125 c storage temperature range .................. C 55 c to 125 c peak solder reflow body temperature ................. 260 c (note 1) order information lga package (weight = 0.70g) 77-lead (9mm 15mm 1.82mm) bga package (weight = 0.83g) 77-lead (9mm 15mm 2.42mm) 1 2 3 4 5 6 7 b c d e f g h j k l a top view v out1 sv in1 mode1 run1 comp1 intv cc1 gnd pgood2 pgood1 intv cc2 pgood3 temp intv cc3 pgood4 clkout fb1 track/ss1 gnd clkin track/ss2 fb2 run2 sgnd track/ss3 fb3 track/ss4 intv cc4 run4 mode2 sv in2 comp2 run3 fb4 mode3 sv in3 comp3 comp4 mode4 sv in4 v in4 v in1 gnd gnd gnd v in3 v in2 v out4 v out3 v out2 t jmax = 125c, jctop = 17c/w, jcbottom = 2.75c/w, jb + ba = 11c/w, ja = 10c/w values per jesd 51-12 pin configuration part number pad or ball finish part marking* package type msl rating temperature range (see note 2) device finish code lt m4643ev#pbf au (rohs) lt m4643v e4 lga 3 C40c to 125c lt m4643iv#pbf au (rohs) lt m4643v e4 lga 3 C40c to 125c lt m4643mpv#pbf au (rohs) lt m4643v e4 lga 3 C55c to 125c lt m4643ey#pbf sac305 (rohs) lt m4643y e1 bga 3 C40c to 125c lt m4643iy#pbf sac305 (rohs) lt m4643y e1 bga 3 C40c to 125c lt m4643mpy#pbf sac305 (rohs) lt m4643y e1 bga 3 C55c to 125c lt m4643iy snpb (63/37) lt m4643y e0 bga 3 C40c to 125c lt m4643 mpy snpb (63/37) lt m4643y e0 bga 3 C55c to 125c consult marketing for parts specified with wider operating temperature ranges. *device temperature grade is indicated by a label on the shipping container. pad or ball finish code is per ipc/jedec j-std-609. ? terminal finish part markings: www.linear.com/leadfree ? recommended lga and bga pcb assembly and manufacturing procedures: www .linear.com/umodule/pcbassembly ? package and t ray drawings: www.linear.com/packaging http://www.linear.com/product/LTM4643#orderinfo LTM4643 4643fb for more information www.linear.com/LTM4643
3 electrical characteristics the l denotes the specifications which apply over the specified internal operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, per the typical application. symbol parameter conditions min typ max units switching regulator section: per channel v in , sv in input dc voltage sv in = v in l 4 20 v v out(range) output voltage range l 0.6 3.3 v v out(dc) output voltage, total variation with line and load c in = 22f, c out = 100f ceramic, r fb = 40.2k, mode = int v cc ,v in = 4v to 20v, i out = 0a to 3a (note 4) l 1.477 1.50 1.523 v v run run pin on threshold v run rising 1.1 1.2 1.3 v i q(svin) input supply bias current v in = 12v, v out = 1.5v, mode = intv cc v in = 12v, v out = 1.5v, mode = gnd shutdown, run = 0, v in = 12v 6 2 11 ma ma a i s(vin) input supply current v in = 12v, v out = 1.5v, i out = 3a 0.45 a i out(dc) output continuous current range v in = 12v, v out = 1.5v (note 4) 0 3 a v out (line)/v out line regulation accuracy v out = 1.5v, v in = 4v to 20v, i out = 0a l 0.01 0.05 %/v v out (load)/v out load regulation accuracy v out = 1.5v, i out = 0a to 3a l 0.5 1.0 % v out(ac) output ripple voltage i out = 0a, c out = 100f ceramic, v in = 12v, v out = 1.5v 5 mv v out(start) turn-on overshoot i out = 0a, c out = 100f ceramic, v in = 12v, v out = 1.5v 30 mv t start turn-on time c out = 100f ceramic, no load, track/ss = 0.01f, v in = 12v, v out = 1.5v 2.5 ms v outls peak deviation for dynamic load load: 0% to 50% to 0% of full load, c out = 47f ceramic, v in = 12v, v out = 1.5v 160 mv t settle settling time for dynamic load step load: 0% to 50% to 0% of full load, c out = 47f ceramic, v in = 12v, v out = 1.5v 40 s i outpk output current limit v in = 12v, v out = 1.5v 3.5 5 a v fb voltage at fb pin i out = 0a, v out = 1.5v, C40c to 125c l 0.593 0.60 0.607 v i fb current at fb pin (note 3) 30 na r fbhi resistor between v out and fb pins 60.05 60.40 60.75 k i track/ss track pin soft-start pull-up current track/ss = 0v 2.5 4 a v in(uvlo) v in undervoltage lockout v in falling v in hysteresis 2.4 2.6 350 2.8 v mv t on(min) minimum on-time (note 3) 40 ns t off(min) minimum off-time (note 3) 70 ns v pgood pgood trip level v fb with respect to set output v fb ramping negative v fb ramping positive C13 7 C10 10 C7 13 % % i pgood pgood leakage 2 a v pgl pgood voltage low i pgood = 1ma 0.02 0.1 v v intvcc internal v cc voltage sv in = 4v to 20v 3.1 3.3 3.4 v v intvcc load reg intv cc load regulation i cc = 0ma to 20ma 0.5 % f osc oscillator frequency 1.2 mhz clkin clkin threshold 0.7 v LTM4643 4643fb for more information www.linear.com/LTM4643
4 1.0v output transient response 1.2v output transient response 1.5v output transient response efficiency vs load current from 5v in (one channel operating) efficiency vs load current from 12v in (one channel operating) dcm mode efficiency from 1.5v out electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTM4643 is tested under pulsed load conditions such that t j t a . the LTM4643e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the full C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the LTM4643i is guaranteed to meet specifications over the full C40c to 125c internal operating temperature range. the LTM4643mp is guaranteed to meet specifications over the full C55c to 125c internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: 100% tested at wafer level. note 4: see output current derating curves for different v in , v out and t a . note 5: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. typical performance characteristics output current (a) 0 60 65 efficiency (%) 70 80 85 90 100 95 1 0.5 1.5 4643 g01 75 3 2 2.5 3.3v out 2.5v out 1.8v out 1.5v out 1.2v out 1.0v out output current (a) 0 55 60 65 efficiency (%) 70 80 85 90 95 1 0.5 1.5 4643 g02 75 3 2 2.5 3.3v out 2.5v out 1.8v out 1.5v out 1.2v out 1.0v out load current (a) 0.001 0 efficiency (%) 20 30 40 100 0.01 4643 g03 10 50 60 70 80 90 10 0.1 1 5v in 12v in v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 1.0v output capacitor = 1 47f ceramic cap load step = 2a to 3a with 1a/s slew rate feed forward cap = 100pf 20s/div 4643 g04 (per channel) v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 1.2v output capacitor = 1 47f ceramic cap load step = 2a to 3a with 1a/s slew rate feed forward cap = 100pf 20s/div 4643 g05 v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 1.5v output capacitor = 1 47f ceramic cap load step = 2a to 3a with 1a/s slew rate feed forward cap = 100pf 20s/div 4643 g06 LTM4643 4643fb for more information www.linear.com/LTM4643
5 typical performance characteristics 1.8v output transient response 2.5v output transient response 3.3v output transient response start-up with no load applied start-up with 3a load applied short-circuit with no load applied v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 2.5v output capacitor = 1 47f ceramic cap load step = 2a to 3a with 1a/s slew rate feed forward cap = 100pf 20s/div 4643 g08 v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 3.3v output capacitor = 1 47f ceramic cap load step = 2a to 3a with 1a/s slew rate feed forward cap = 100pf 20s/div 4643 g09 i in 0.5a/div v out 0.5v/div v in = 12v v out = 1.5v input capacitor = 1 22f ceramic cap output capacitor = 1 47f ceramic cap soft start = 0.1f 5ms/div 4643 g10 i in 0.5a/div v out 0.5v/div v in = 12v v out = 1.5v input capacitor = 1 22f ceramic cap output capacitor = 1 47f ceramic cap soft start = 0.1f 5ms/div 4643 g11 i in 0.5a/div v out 0.5v/div v in = 12v v out = 1.5v input capacitor = 1 22f ceramic cap output capacitor = 1 47f ceramic cap 5ms/div 4643 g12 v in = 12v v out = 1.8v output capacitor = 1 47f ceramic cap load step = 2a to 3a with 1a/s slew rate feed forward cap = 100pf 20s/div 4643 g07 v out 50mv/div ac-coupled load step 1a/div short-circuit with 3a load applied short-circuit with 3a load applied i in 0.5a/div v out 0.5v/div v in = 12v v out = 1.5v input capacitor = 1 22f ceramic cap output capacitor = 1 47f ceramic cap 20s/div 4643 g13 i in 0.5a/div v out 0.5v/div v in = 12v v out = 1.5v input capacitor = 1 22f ceramic cap output capacitor = 1 47f ceramic cap 20s/div 4643 g14 output ripple v out 5mv/div ac-coupled 350khz bandwidth v in = 12v v out = 1.5v output capacitor = 2 47f ceramic cap 2s/div 4643 g15 LTM4643 4643fb for more information www.linear.com/LTM4643
6 pin functions v out1 ( a1, a2, a3), v out2 ( c1, d1, d2), v out3 (f1, g1, g2 ), v out4 ( j1, k1, k2): power output pins of each switching mode regulator channel. apply output load between these pins and gnd pins. recommend placing output decoupling capacitance directly between these pins and gnd pins. see the applications information section for paralleling outputs. gnd ( a4-a5, b1-b2, c5, d3-d5, e1-e2, f5, g3-g5, h1-h2, j5, k3-k4, l1-l2): power ground pins for both input and output returns. use large pcb copper areas to connect all gnd together. v in1 ( b3, b4), v in2 ( e3, e4), v in3 ( h3, h4), v in4 ( l3, l4): power input pins connect to the drain of the internal top mosfet for each switching mode regulator channel. apply input voltages between these pins and gnd pins. recommend placing input decoupling capacitance directly between each of v in pins and gnd pins. pgood1, pgood2, pgood3, pgood4 ( c3, c2, f2, j2): output power good with open-drain logic of each switching mode regulator channel. pgood is pulled to ground when the voltage on the fb pin is not within 10% of the internal 0.6v reference. clkout (j3): output clock signal for polyphase ? opera- tion of the module. the phase of clkout with respect to clkin is set to 180 . clkouts peak-to-peak amplitude is intv cc to gnd. see the application information section for details. strictly output; do not drive this pin. intv cc1 , intv cc2 , intv cc3 , intv cc4 ( c4, f4, j4, k5): internal 3.3v regulator output of each switching mode regulator channel. the internal power drivers and con - trol circuits are powered from this voltage. each pin is internally decoupled to gnd with 1f low esr ceramic capacitor already. sv in1 , sv in2 , sv in , sv in4 ( b5, e5, h5, l5): signal v in . filtered input voltage to the internal 3.3v regulator for the control circuitry of each switching mode regulator channel. tie this pin to the v in pin respectively in most applications. connect sv in to an external voltage supply of at least 4v which must also be greater than v out . track/ss1, track/ss2, track/ss3, track/ss4 (a6, d6, g6, k6): output tracking and soft-start pin of each switching mode regulator channel. allows the user to control the rise time of the output voltage. putting a volt- age below 0.6v on this pin bypasses the internal reference input to the error amplifier, instead it servos the fb pin to match the track voltage. above 0.6v, the tracking function stops and the internal reference resumes control of the error amplifier. there s an internal 2.5a pull-up current from intv cc on this pin, so putting a capacitor here provides soft-start function. mode1, mode2, mode3, mode4 ( b6, e6, h6, l6): operation mode select for each switching mode regula - tor channel. tie this pin to intv cc to force continuous synchronous operation at all output loads. tying it to sgnd enables discontinuous current mode operation at light loads. do not leave floating. run1, run2, run3, run4 ( c6, f6, j6, k7): run control input of each switching mode regulator channel. enable regulator operation by tying the specific run pin above 1.2v. pulling it below 1.1v shuts down the respective regulator channel. do not leave floating. fb1, fb2, fb3, fb4 ( a7, d7, g7, j7): the negative input of the error amplifier for each switching mode regulator channel. internally, this pin is connected to v out of each channel with a 60.4k precision resistor. different output voltages can be programmed with an additional resistor between the fb and gnd pins. in polyphase operation, tying the fb pins together allows for parallel operation. see the applications information section for details. package row and column labeling may vary among module products. review each package layout carefully. LTM4643 4643fb for more information www.linear.com/LTM4643
7 pin functions comp1, comp2, comp3, comp4 ( b7, e7, h7, l7): cur- rent control threshold and error amplifier compensation point of each switching mode regulator channel. the internal current comparator threshold is proportional to this voltage. t ie the comp pins together for parallel opera - tion. the device is internally compensated. clkin ( c7): external synchronization input to phase detector of the module. this pin is internally terminated to sgnd with 20k . the phase-locked loop will force the channel 1 turn-on signal to be synchronized with the rising edge of the clkin signal. channel 2, channel 3 and channel 4 will also be synchronized with the rising edge of the clkin signal with a pre-determined phase shift. see the applications information section for details. sgnd ( f7 ): signal ground connection. sgnd is connected to gnd internally through single point. use a separated sgnd ground copper area for the ground of the feedback resistor and other components connected to signal pins. a second connection between the pgnd plane and sgnd plane is recommended on the backside of the pcb under - neath the module. temp ( f3): onboard temperature diode for monitoring the vbe junction voltage change with temperature. see the applications information section. LTM4643 4643fb for more information www.linear.com/LTM4643
8 block diagram 4643 bd power control clkout fb1 clkin mode1 track/ss1 run1 comp1 intv cc1 internal filter internal comp v out1 1f 0.22f 1h 100k 100k 100k 100k 10f 47f freq1 133k 60.4k 60.4k 0.1f v in 4v to 20v v out1 1.2v 3a intv cc1 pgood1 sv in1 v in1 v out1 gnd sgnd gnd power control fb2 mode2 track/ss2 run2 comp2 intv cc2 internal filter internal comp v out2 1f 0.22f 1h 10f 47f freq2 133k 60.4k 40.2k 0.1f v in v out2 1.5v 3a intv cc2 pgood2 sv in2 v in2 v out2 gnd power control fb3 mode3 track/ss3 run3 comp3 intv cc3 internal filter internal comp v out3 1f 0.22f 1h 10f 47f freq3 133k 60.4k 30.1k 0.1f v in v out3 1.8v 3a intv cc3 pgood3 sv in3 v in3 v out3 gnd power control fb4 mode4 track/ss4 run4 comp4 intv cc4 internal filter internal comp v out4 1f 0.22f 1h 10f 47f 1f freq4 133k 60.4k 90.9k 0.1f v in v out4 1v 3a intv cc4 pgood4 sv in4 v in4 v out4 gnd temp clkout clkout clkin clkout clkin clkout clkin 1f 1f 1f LTM4643 4643fb for more information www.linear.com/LTM4643
9 symbol parameter conditions min typ max units c in external input capacitor requirement (v in = 4v to 20v, v out = 1.5v) i out = 3a 4.7 10 f c out external output capacitor requirement (v in = 4v to 20v, v out = 1.5v) i out = 3a 22 47 f decoupling requirements operation the LTM4643 is a quad output standalone non-isolated switch mode dc/dc power supply in 9mm? ? 15mm ?1.82mm ultrathin package. it has four separate regula - tor channels with each of them capable of delivering up to 3a continuous output current with few external input and output capacitors. each regulator provides precisely regulated output voltage programmable from 0.6v to 3.3v via a single external resistor over 4v to 20v input voltage range. with an external bias voltage, this module can operate from an input voltage as low as 2.375v . the typical application schematic is shown in figure?29. the LTM4643 integrates four separate constant frequency controlled on-time valley current mode regulators, power mosfets, inductors, and other supporting discrete com - ponents. the typical switching frequency is set to 1.2mhz . for switching noise-sensitive applications, the module regulator can be externally synchronized to a clock from 850khz to 1.5mhz. see the applications information section. with current mode control and internal feedback loop compensation, the LTM4643 module has sufficient stabil - ity margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. current mode control provides the flexibility of paralleling any of the separate regulator channels with accurate cur- rent sharing. with a built-in clock interleaving between regulator channels, the LTM4643 can easily be configured for 2+2, 3+1 or 4 channels parallel operation providing more design flexibility for multirail pol applications. fur - thermore, the LTM4643 has clkin and clkout pins for frequency synchronization or polyphasing multiple devices which allow up to 8 phases cascaded to run simultaneously. current mode control also provides cycle-by-cycle fast current monitoring. foldback current limiting is provided in an overcurrent condition to reduce the inductor valley current to approximately 40% of the original value when v fb drops. an internal overvoltage and undervoltage comparators pull the open-drain pgood output low if the output feedback voltage exits a 10% window around the regulation point. continuous conduction mode (ccm) operation is forced during ov and uv conditions except during start-up when the track pin is ramping up to 0.6v. pulling the run pin below 1.1v forces the controller into its shutdown state, turning off both power mosfets and most of the internal control circuitry. at light load cur - rents, discontinuous conduction mode (dcm) operation can be enabled to achieve higher efficiency compared to continuous conduction mode (ccm) by setting the mode pin to sgnd. the track/ss pin is used for power supply tracking and soft-start programming. see the applications information section. a temperature diode is included inside the module to moni - tor the temperature of the module. see the applications information section for details. (per channel) LTM4643 4643fb for more information www.linear.com/LTM4643
10 applications information the typical LTM4643 application circuit is shown in figure? 29. external component selection is primarily determined by the input voltage, the output voltage and the maximum load current. refer to t able 6 for specific external capacitor requirements for a par ticular application. v in to v out step-down ratios there are restrictions in the maximum v in and v out step- down ratio that can be achieved for a given input voltage due to the minimum off-time and minimum on-time limits of each regulator. the minimum off-time limit imposes a maximum duty cycle which can be calculated as: d max = 1 C t off(min) ? f sw where t off(min) is the minimum off-time, 70ns typical for LTM4643, and f sw is the switching frequency. conversely the minimum on-time limit imposes a minimum duty cycle of the converter which can be calculated as: d min = t on(min) ? f sw where t on(min) is the minimum on-time, 40ns typical for LTM4643. in the rare cases where the minimum duty cycle is surpassed, the output voltage will still remain in regulation, but the switching frequency will decrease from its programmed value. note that additional thermal derating may be applied. see the thermal considerations and output current derating section in this data sheet. output voltage programming the pwm controller has an internal 0.6v reference voltage. as shown in the block diagram, a 60.4k internal feedback resistor connects each regulator channel from v out pin to fb pin. adding a resistor r fb from fb pin to gnd programs the output voltage: r fb = 60.4k v out 0.6 ? 1 table 1. v fb resistor table vs various output voltages v out (v) 0.6 1.0 1.2 1.5 1.8 2.5 3.3 r fb (k) open 90.9 60.4 40.2 30.1 19.1 13.3 for parallel operation of n channels, use the following equation can be used to solve for r fb . tie the v out and the fb and comp pins together for each paralleled output with a single resistor to gnd as determined by: r fb = 60.4k n ? ? ? ? ? ? ? ? v out 0.6 ? 1 ? ? ? ? ? ? ? ? input decoupling capacitors the LTM4643 module should be connected to a low ac- impedance dc source. for each regulator channel, a 10f input ceramic capacitor is recommended for rms ripple current decoupling. a bulk input capacitor is only needed when the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. the bulk capacitor can be an electrolytic aluminum capaci - tor or polymer capacitor. without considering the inductor ripple current, the rms current of the input capacitor can be estimated as : i cin(rms) = i out(max ) % ? d ? (1 ? d) where % is the estimated efficiency of the power module. output decoupling capacitors with an optimized high frequency, high bandwidth design, only single piece of low esr output ceramic capacitor is required for each regulator channel to achieve low output voltage ripple and very good transient response. additional output filtering may be required by the system designer, if further reduction of output ripples or dynamic transient spikes is required. table 6 provides a reference matrix show - ing transient performance for different output capacitor con - figurations. multiphase operation will reduce effective out - put ripple as a function of the number of phases. application note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance will be more a function of stability and transient response. the ltpowercad ? design tool is available to download online for output ripple, stability and transient response analysis and calculating the output ripple reduction as the number of phases implemented increases by n times. LTM4643 4643fb for more information www.linear.com/LTM4643
11 applications information discontinuous conduction mode (dcm) in applications where low output ripple and high efficiency at intermediate current are desired, discontinuous con - duction mode (dcm) should be used by connecting the mode pin to sgnd. at light loads the internal current comparator may remain tripped for several cycles and force the top mosfet to stay off for several cycles, thus skipping cycles. the inductor current does not reverse in this mode. force continuous conduction mode (ccm) in applications where fixed frequency operation is more critical than low current efficiency , and where the lowest output ripple is desired, forced continuous conduction mode operation should be used. forced continuous opera - tion can be enabled by tying the mode pin to intv cc . in this mode, inductor current is allowed to reverse during low output loads, the comp voltage is in control of the current comparator threshold throughout, and the top mosfet always turns on with each oscillator pulse. during start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4643s output voltage is in regulation. operating frequency the operating frequency of the lt m4643 is optimized to achieve the compact package size and the minimum output ripple voltage while still keeping high efficiency. the default operating frequency is internally set to 1.2mhz . in most applications, no additional frequency adjusting is required. if any operating frequency other than 1.2mhz is required by application, the module regulator can be externally synchronized to a clock from 850khz to 1.5mhz. please note, a minimum switching frequency is required for given v in , v out operating conditions to keep a maxi - mum peak-to-peak inductor ripple current below 2a for the lt m4643 . the peak-to-peak inductor ripple current can be calculated as: i pk ? pk = v out f s (mhz) ? v in C v out v out the maximum 2a peak-to-peak inductor ripple current is enforced due to the nature of the valley current mode control to maintain output voltage regulation at no load. frequency synchronization and clock in the power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. this allows all internal top mosfet turn-on to be locked to the rising edge of the same external clock. the external clock frequency range must be within 30% around the 1.2mhz set frequency. a pulse detection circuit is used to detect a clock on the clkin pin to turn on the phase-locked loop. the pulse width of the clock has to be at least 100ns. the clock high level must be above 2v and clock low level below 0.3v. during the start-up of the regulator, the phase-locked loop function is disabled. multichannel parallel operation for loads that demand more than 3a of output current, the LTM4643 multiple regulator channels can be easily paralleled to provide more output current without increas - ing input and output voltage ripples. the LTM4643 has preset built-in phase shift between each two of the four regulator channels which is suitable to employ a 2+2, 3+1 or 4 channels parallel operation. t able 2 gives the phase difference between regulator channels. table 2. phase difference between regulator channels channel ch1 ch2 ch3 ch4 phase difference 180 90 180 figure?1 shows a 2+2 and a 4-channels parallel concept schematic for clock phasing. a multiphase power supply significantly reduces the amount of ripple current in both the input and output ca - pacitors. the rms input ripple current is reduced by, and the effective ripple frequency is multiplied by , the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). the output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design. LTM4643 4643fb for more information www.linear.com/LTM4643
12 applications information figure?2. normalized rms ripple current for single phase or polyphase applications the LTM4643 device is an inherently current mode con- trolled device, so parallel modules will have very good current sharing. this will balance the thermals on the design. please tie the run, track/ss, fb and comp pins of each paralleling channel together. figure?31 and figure?32 show an example of parallel operation and pin connection. input rms ripple current cancellation application note 77 provides a detailed explanation of multiphase operation. the input rms ripple current can - cellation mathematical derivations are presented, and a graph is displayed representing the rms ripple current reduction as a function of the number of interleaved phases. figure?2 shows this graph. soft-start and output voltage t racking the track/ss pin provides a means to either soft-start of each regulator channel or track it to a different power supply. a capacitor on the track/ss pin will program the ramp rate of the output voltage. an internal 2.5a current source will charge up the external soft-start capacitor duty cycle (v out /v in ) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4643 f02 1-phase 2-phase 4-phase rms input ripple current dc load current figure?1. 2+2 and 4 channels parallel concept schematic 4643 f01 fb1 track/ss1 comp1 run1 v out1 ch1 (0) fb2 track/ss2 comp2 run2 v out2 LTM4643 6a 6a ch2 (180) 180 fb3 track/ss3 comp3 run3 v out3 ch3 (0) fb4 track/ss4 comp4 run4 v out4 ch4 (180) 180 fb1 track/ss1 comp1 run1 v out1 ch1 (0) fb2 track/ss2 comp2 run2 v out2 LTM4643 12a ch2 (180) 180 fb3 track/ss3 comp3 run3 v out3 ch3 (270) fb4 track/ss4 comp4 run4 v out4 ch4 (90) 180 90 LTM4643 4643fb for more information www.linear.com/LTM4643
13 applications information towards the intv cc voltage. when the track/ss voltage is below 0.6v, it will take over the internal 0.6v reference voltage to control the output voltage. the total soft-start time can be calculated as: t ss = 0.6 ? c ss 2.5a where c ss is the capacitance on the track/ss pin. cur- rent foldback and forced continuous mode are disabled during the soft-start process. output voltage tracking can also be programmed externally using the track/ss pin of each regulator channel. the output can be tracked up and down with another regula - tor. figure? 3 and figure? 4 show an example waveform and schematic of a ratiometric tracking where the slave regulator s (v out2 , v out3 and v out4 ) output slew rate is proportional to the masters (v out1 ). since the slave regulators track/ss is connected to the master s output through a r tr(top) /r tr(bot) resistor divider and its voltage used to regulate the slave output 4643 f04 v in1 sv in1 run1 intv cc1 mode1 v out1 fb1 comp1 track/ss1 pgood1 ch1 c ss 0.1f r fb1 13.3k v in 5v to 20v r tr2(top) 60.4k 3.3v/3a 2.5v/3a 1.8v/3a 1.2v/3a v in2 sv in2 run2 intv cc2 mode2 v out2 fb2 comp2 track/ss2 pgood2 ch2 r fb2 19.1k v in3 sv in3 run3 intv cc3 mode3 v out3 fb3 comp3 track/ss3 pgood3 ch3 r fb3 30.1k v in4 sv in4 run4 intv cc4 mode4 v out4 fb4 comp4 track/ss4 pgood4 ch4 r fb4 60.4k r tr2(bot) 13.3k r tr3(top) 60.4k r tr3(bot) 13.3k r tr4(top) 60.4k r tr4(bot) 13.3k 4643 f03 time output voltage v out4 = 1.2v v out3 = 1.8v v out2 = 2.5v v out1 = 3.3v figure?3. output ratiometric tracking waveform figure?4. output ratiometric tracking schematic voltage when track/ss voltage is below 0.6v, the slave output voltage and the master output voltage should satisfy the following equation during the start-up. v out(sl) ? r fb(sl) r fb(sl) + 60.4k = v out(ma ) ? r tr(bot) r tr(top) + r tr(bot) LTM4643 4643fb for more information www.linear.com/LTM4643
14 applications information the r fb(sl) is the feedback resistor and the r tr(top) / r tr(bot) is the resistor divider on the track/ss pin of the slave regulator, as shown in figure?4. following the upper equation, the masters output slew rate (mr) and the slaves output slew rate (sr) in volts/ time is determined by: mr sr = r fb(sl) r fb(sl) + 60.4k r tr(bot) r tr(top) + r tr(bot) for example, v out(ma) = 3.3v , mr = 3.3v/ms and v out(sl) = 1.2v , sr = 1.2v/ms as v out1 and v out4 shown in figure? 4. from the equation, we could solve out that r tr4(top) = 60.4k and r tr4(bot) = 13.3k is a good com - bination. follow the same equation, we can get the same r tr(top) /r tr(bot) resistor divider value for v out2 and v out3 . the track pins will have the 2.5a current source on when a resistive divider is used to implement tracking on that specific channel. this will impose an offset on the track pin input. smaller value resistors with the same ratios as the resistor values calculated from the above equation can be used. for example, where the 60.4k is used then a 6.04k can be used to reduce the track pin offset to a negligible value. the coincident output tracking can be recognized as a special ratiometric output tracking which the masters output slew rate (mr) is the same as the slaves output slew rate (sr), as waveform shown in figure?5. from the equation we could easily find out that, in the coincident tracking, the slave regulators track/ss pin resistor divider is always the same as its output voltage divider. r fb(sl) r fb(sl) + 60.4k = r tr(bot) r tr(top) + r tr(bot) for example, r tr4(top) = 60.4k and r tr4(bot) = 60.4k is a good combination for coincident tracking for v out(ma) = 3.3v and v out(sl) = 1.2v application. power good the pgood pins are open drain pins that can be used to monitor each valid output voltage regulation. this pin monitors a 10% window around the regulation point. a resistor can be pulled up to a particular supply voltage for monitoring. to prevent unwanted pgood glitches dur - ing transients or dynamic v out changes, the LTM4643s pgood falling edge includes a blanking delay of approxi - mately 52 switching cycles. stability compensation the lt m4643 module internal compensation loop of each regulator channel is designed and optimized for low esr ceramic output capacitors only application. table 6 is provided for most application requirements. an optional 100pf phase boost capacitor could help to boost up the phase margin in all ceramic output capacitors application. the ltpowercad design tool is available to download for control loop optimization. run enable pulling the run pin of each regulator channel to ground forces the regulator into its shutdown state, turning off both power mosfets and most of its internal control circuitry. bringing the run pin above 0.7v turns on the internal reference only, while still keeping the power mosfets off. further increasing the run pin voltage above 1.2v will turn on the entire regulator channel. figure?5. output coincident tracking waveform 4643 f05 time output voltage v out4 = 1.2v v out3 = 1.8v v out2 = 2.5v v out1 = 3.3v LTM4643 4643fb for more information www.linear.com/LTM4643
15 applications information pre-biased output start-up there may be situations that require the power supply to start up with some charge on the output capacitors. the LTM4643 can safely power up into a pre-biased output without discharging it. the LTM4643 accomplishes this by forcing discontinuous mode (dcm) operation until the track/ss pin voltage reaches 0.6v reference voltage. this will prevent the bg from turning on during the pre-biased output start-up which would discharge the output. do not pre-bias LTM4643 with an output voltage higher than intv cc (3.3v). overtemperature protection the internal overtemperature protection monitors the junc - tion temperature of the module. if the junction temperature reac hes approximately 160c , both power switches will be turned off until the temperature drops about 15c cooler. low input application the LTM4643 module has a separate sv in pin for each regulator channel which makes it compatible with opera - tion from an input voltage as low as 2.375v. the sv in pin is the signal input of the regulator control circuitry while the v in pin is the power input which directly connected to the drain of the top mosfet. in most application with input voltage ranges from 4v to 20v, connect the sv in pin directly to the v in pin of each regulator channel. an optional filter, consisting of a resistor ( 1 to 10 ) between sv in and v in ground, can be placed for additional noise immunity. this filter is not necessary in most cases if good pcb layout practices are followed (see figure?28). in a low input voltage (2.375v to 4v) application, or to reduce power dissipation by the internal bias ldo, connect sv in to an external voltage higher than 4v with a 0.1f local bypass capacitor. figure?30 shows an example of a low input voltage application. please note, sv in voltage cannot go below v out voltage. temperature monitoring a diode connected pnp transistor is used for the temp monitor function by monitoring its voltage over tempera - ture. the temperature dependence of this diode voltage can be understood in the equation : v d = nv t ln i d i s ? ? ? ? ? ? ? ? ? ? where v t is the thermal voltage (kt/q), and n, the ideality factor, is 1 for the diode connected pnp transistor be - ing used in the LTM4643. i s is expressed by the typical empirical equation: i s = i 0 exp Cv g0 v t ? ? ? ? ? ? ? ? ? ? where i 0 is a process and geometry dependent current, (i 0 is typically around 20k orders of magnitude larger than i s at room temperature) and v g0 is the band gap voltage of 1.2v extrapolated to absolute zero or C273c. if we take the i s equation and substitute into the v d equa- tion, then we get: v d = v g0 C kt q ? ? ? ? ? ? ? ? ? ? ln i 0 i d ? ? ? ? ? ? ? ? ? ? , v t = kt q the expression shows that the diode voltage decreases (linearly if i 0 were constant) with increasing temperature and constant diode current. figure?6 shows a plot of v d vs temperature over the operating temperature range of the LTM4643. if we take this equation and differentiate it with respect to temperature t, then: dv d dt = C v g0 C v d t this dv d /dt term is the temperature coefficient equal to about C2mv /k or C2mv/c. the equation is simplified for the first order derivation. solving for t, t = C(v g0 C v d )/(dv d /dt) provides the temperature. LTM4643 4643fb for more information www.linear.com/LTM4643
16 applications information 1st example : figure? 6 for 27 c , or 300k the diode voltage is 0.598v, thus, 300k = C(1200mv C 598mv)/ C2.0 mv/k) 2nd example : figure? 6 for 75c , or 350k the diode voltage is 0.50v, thus, 350k = C(1200mv C 500mv)/ C2.0mv/k) converting the kelvin scale to celsius is simply taking the kelvin temp and subtracting 273 from it. a typical forward voltage is given in the electrical charac - teristics section of the data sheet, and figure? 6 is the plot of this for ward voltage. measure this for ward voltage at 27c to establish a reference point. then using the above expression while measuring the forward voltage over temperature will provide a general temperature monitor. connect a resistor between temp and v in to set the cur - rent to 100a. see figure?31 for an example. the motivation for providing these thermal coefficients in found in jesd 51- 12 (guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the module regulator s thermal performance in their appli - cation at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin con - figuration section are in-and-of themselves not relevant to providing guidance of thermal performance ; instead, the derating curves provided in this data sheet can be used in a manner that yields insight and guidance pertaining to ones application-usage, and can be adapted to correlate thermal performance to ones own application. the pin configuration section typically gives four thermal coefficients explicitly defined in jesd 51-12; these coef - ficients are quoted or paraphrased below: 1. ja , the thermal resistance from junction to ambi - ent, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd 51-9 defined test board, which does not reflect an actual application or viable operating condition. 2. jcbottom , the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the page. in the typical module regulator, the bulk of the heat flows out the bottom of the pack - age, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions don t generally match the user s application. 3. jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. as the electrical connections of the typical module regulator are on the bottom of the figure?6. diode voltage v d vs temperature t(c) temperature (c) ?50 ?25 0.3 diode voltage (v) 0.5 0.8 0 50 75 0.4 0.7 0.6 25 100 4643 f06 125 i d = 100a thermal considerations and output current derating the thermal resistances reported in the pin configura - tion section of the data sheet are consistent with those parameters defined by jesd 51- 12 and are intended for use with finite element analysis (fea) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation per- formed on a module package mounted to a hardware test board: defined by jesd 51-9 ( test boards for area array surface mount package thermal measurements ). LTM4643 4643fb for more information www.linear.com/LTM4643
17 figure?7. graphical representation of jesd 51-12 thermal coefficients 4643 f07 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient thermal resistance components case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions don t generally match the user s application. 4. jb , the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resis - tance where almost all of the heat flows through the bottom of the module regulator and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package. a graphical representation of the aforementioned ther - mal resistances is given in figure?7 ; blue resistances are contained within the module regulator, whereas green resistances are external to the module package. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by jesd 51-12 or provided in the pin configuration section replicates or conveys normal operating conditions of a module regulator. for example, in normal board-mounted applications, never does 100% of the devices total power loss (heat) thermally conduct exclusively through the top or exclusively through bot - tom of the module packageas the standard defines for jctop and jcbottom , respectively. in practice, power applications information loss is thermally dissipated in both directions away from the package granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. within the LTM4643, be aware there are multiple power devices and components dissipating power, with a con - sequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. t o reconcile this complication without sacrificing modeling simplicity but also, not ignoring practical realitiesan approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) initially, fea software is used to accurately build the mechanical geometry of the LTM4643 and the specified pcb with all of the cor - rect material coefficients along with accurate power loss sour ce definitions ; (2) this model simulates a software- defined jedec environment consistent with jesd 51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec-defined thermal resistance values; (3) the model and fea software is used to evaluate the LTM4643 with heat sink and airflow ; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss LTM4643 4643fb for more information www.linear.com/LTM4643
18 as that which was simulated. an outcome of this process and due diligence yields the set of derating curves shown in this data sheet. the 1v to 3.3v power loss curves in figures 8 to 13 can be used in coordination with the load current derating curves in figures 14 to 25 for calculating an approximate ja thermal resistance for the LTM4643 with various heat sinking and airflow conditions. the power loss curves are taken at room temperature, and are increased with a multi - plicative factor according to the junction temperature. this approximate factor is 1.3 for 120c . the derating curves are plotted with the output current starting at 12a and the ambient temperature starting at 30c . these are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal mod - eling analysis. the junction temperatures are monitored while ambient temperature is increased with and without air flow . the power loss increase with ambient temperature change is factored into the derating curves. the junctions are maintained at 120c maximum while lowering output current or power with increasing ambient temperature. the decreased output current will decrease the internal module loss as ambient temperature is increased. the monitored junction temperature of 120c minus the ambient operat - ing temperature specifies how much module temperature rise can be allowed. as an example, in figure?19 the load current is derated to 10a at ~67c with 200lfm of airflow and no heat sink and the power loss for the 12v to 1.5v at 10a output is about 4.5w . the 4.5w loss is calculated with 4 times the 0.87w room temperature loss from the 12v to 1.5v power loss curve each channel at 2.5a, and the 1.3 multiplying factor at 120c junction. if the 67c ambient temperature is subtracted from the 120 c junction temperature, then the difference of 53c divided by 4.5w equals 11.7c/w ja thermal resistance. table 3 specifies a 12c /w value which is very close. tables 3 to?5 provide equivalent thermal resistances for the different outputs with and without airflow and heat sinking. the derived thermal resistances in tables 3 to 6 for the various condi - tions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. room temperature power loss can be derived from the efficiency curves in the t ypical performance characteristics section and adjusted with the above junction temperature multiplicative factor. the printed circuit board is a 1.6mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. the pcb dimensions are 95mm 76mm. the 12a represents all four channels in parallel at 3a each. the four parallel channels have their currents reduced at the same rate to develop an equivalent ja circuit evalu - ation with thermal couples or ir camera used to validate the thermal resistance values. maximum operating ambient t emperature figures 26 and 27 display the maximum power loss allowance cur ves vs ambient temperature with various heat sinking and airflow conditions. this data was derived from the thermal impedance generated by various ther - mal derating examinations with the junction temperature measured at 120c . this maximum power loss limitation serves as a guideline when designing multiple output rails with different voltages and currents by calculating the total power loss. for example, to determine the maximum ambient tem - perature when v out1 = 2.5v at 0.6a, v out2 = 3.3v at 3a, v out3 ?= 1.8v at 1a, v out4 = 1.2v at 3a, without a heat sink and 400lfm airflow, simply add up the total power loss for each channel read from figure? 8 to figure? 13 which in this example equals 3.0w , then multiply by the 1.3 coefficient for 120c junction temperature and com - pare the total power loss number, 3.9w , with figure?26. figure? 26 indicates with a 3.9w total power loss, the maximum ambient temperature for this particular ap - plication is around 77c . also from figure?26, it is easy to determine with a 3.4w total power loss, the maximum ambient temperature is around 63c with no airflow and 73c with 200lfm airflow. applications information LTM4643 4643fb for more information www.linear.com/LTM4643
19 figure?8. power loss at 1.0v output, (each channel, 25c) applications information load current (a) 0 0 power loss (w) 0.6 1.5 1.4 1 4643 f08 0.2 0.4 0.8 1.2 1.0 0.5 1.3 0.1 0.3 0.7 1.1 0.9 3 2 0.5 1.5 2.5 5v in 12v in load current (a) 0 0 power loss (w) 0.6 1.5 1.4 1 4643 f09 0.2 0.4 0.8 1.2 1.0 0.5 1.3 0.1 0.3 0.7 1.1 0.9 3 2 0.5 1.5 2.5 5v in 12v in load current (a) 0 0 power loss (w) 0.6 1.5 1.4 1 4643 f10 0.2 0.4 0.8 1.2 1.0 0.5 1.3 0.1 0.3 0.7 1.1 0.9 3 2 0.5 1.5 2.5 5v in 12v in load current (a) 0 0 power loss (w) 0.6 1.5 1.4 1 4643 f11 0.2 0.4 0.8 1.2 1.0 0.5 1.3 0.1 0.3 0.7 1.1 0.9 3 2 0.5 1.5 2.5 5v in 12v in load current (a) 0 0 power loss (w) 0.6 1.5 1.4 1 4643 f12 0.2 0.4 0.8 1.2 1.0 0.5 1.3 0.1 0.3 0.7 1.1 0.9 3 2 0.5 1.5 2.5 5v in 12v in load current (a) 0 0 power loss (w) 0.6 1.5 1.4 1 4643 f13 0.2 0.4 0.8 1.2 1.0 0.5 1.3 0.1 0.3 0.7 1.1 0.9 3 2 0.5 1.5 2.5 5v in 12v in figure?9. power loss at 1.2v output, (each channel, 25c) figure?10. power loss at 1.5v output, (each channel, 25c) figure?11. power loss at 1.8v output, (each channel, 25c) figure?12. power loss at 2.5v output, (each channel, 25c) figure?13. power loss at 3.3v output, (each channel, 25c) LTM4643 4643fb for more information www.linear.com/LTM4643
20 applications information ambient temperature (c) 30 0 10 14 12 4643 f18 4 2 8 6 120 40 80 100 60 50 90 110 70 0lfm 200lfm 400lfm max load current (a) ambient temperature (c) 30 0 max load current (a) 10 14 12 4643 f19 4 2 8 6 120 40 80 100 60 50 90 110 70 0lfm 200lfm 400lfm ambient temperature (c) 30 0 10 14 12 4643 f16 4 2 8 6 120 40 80 100 60 50 90 110 70 0lfm 200lfm 400lfm max load current (a) ambient temperature (c) 30 0 10 14 12 4643 f17 4 2 8 6 120 40 80 100 60 50 90 110 70 0lfm 200lfm 400lfm max load current (a) ambient temperature (c) 30 0 max load current (a) 10 14 12 4643 f20 4 2 8 6 120 40 80 100 60 50 90 110 70 0lfm 200lfm 400lfm figure?14. 5v in to 1.0v out derating curve, 4-channel paralleled, no heat sink ambient temperature (c) 30 0 10 14 12 4643 f14 4 2 8 6 120 40 80 100 60 50 90 110 70 0lfm 200lfm 400lfm max load current (a) ambient temperature (c) 30 0 10 14 12 4643 f15 4 2 8 6 120 40 80 100 60 50 90 110 70 0lfm 200lfm 400lfm max load current (a) figure?15. 12v in to 1.0v out derating curve, 4-channel paralleled, no heat sink figure?16. 5v in to 1.0v out derating curve, 4-channel paralleled, bga heat sink figure?17. 12v in to 1.0v out derating curve, 4-channel paralleled, bga heat sink figure?18. 5v in to 1.5v out derating curve, 4-channel paralleled, no heat sink figure?19. 12v in to 1.5v out derating curve, 4-channel paralleled, no heat sink figure?20. 5v in to 1.5v out derating curve, 4-channel paralleled, bga heat sink LTM4643 4643fb for more information www.linear.com/LTM4643
21 figure?21. 12v in to 1.5v out derating curve, 4-channel paralleled, bga heat sink figure?22. 5v in to 3.3v out derating curve, 4-channel paralleled, no heat sink figure?23. 12v in to 3.3v out derating curve, 4-channel paralleled, no heat sink figure?24. 5v in to 3.3v out derating curve, 4-channel paralleled, bga heat sink ambient temperature (c) 30 0 max load current (a) 10 14 12 4643 f23 4 2 8 6 120 40 80 100 60 50 90 110 70 0lfm 200lfm 400lfm ambient temperature (c) 30 0 max load current (a) 10 14 12 4643 f22 4 2 8 6 120 40 80 100 60 50 90 110 70 0lfm 200lfm 400lfm ambient temperature (c) 30 0 max load current (a) 10 14 12 4643 f21 4 2 8 6 120 40 80 100 60 50 90 110 70 0lfm 200lfm 400lfm ambient temperature (c) 30 0 max load current (a) 10 14 12 4643 f24 4 2 8 6 120 40 80 100 60 50 90 110 70 0lfm 200lfm 400lfm applications information figure?25. 12v in to 3.3v out derating curve, 4-channel paralleled, bga heat sink figure?26. power loss allowance vs. ambient temperature, no heat sink figure?27. power loss allowance vs. ambient temperature, bga heat sink ambient temperature (c) 30 0 max load current (a) 10 14 12 4643 f25 4 2 8 6 120 40 80 100 60 50 90 110 70 0lfm 200lfm 400lfm ambient temperature (c) 30 0 power loss allowance (w) 8 10 9 4643 f26 4 2 1 5 3 7 6 120 40 80 100 60 50 90 110 70 0lfm 200lfm 400lfm ambient temperature (c) 30 0 power loss allowance (w) 8 10 9 4643 f27 4 2 1 5 3 7 6 120 40 80 100 60 50 90 110 70 0lfm 200lfm 400lfm LTM4643 4643fb for more information www.linear.com/LTM4643
22 applications information table 3. 1.0v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figures 14,15 5, 12 figure?8 0 none 14.5 figures 14, 15 5, 12 figure?8 200 none 12 figures 14, 15 5, 12 figure?8 400 none 11 figures 16, 17 5, 12 figure?8 0 bga heat sink 13.5 figures 16, 17 5, 12 figure?8 200 bga heat sink 10 figures 16, 17 5, 12 figure?8 400 bga heat sink 9 table 4. 1.5v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figures 18, 19 5, 12 figure?10 0 none 14.5 figures 18, 19 5, 12 figure?10 200 none 12 figures 18, 19 5, 12 figure?10 400 none 11 figures 20, 21 5, 12 figure?10 0 bga heat sink 13.5 figures 20, 21 5, 12 figure?10 200 bga heat sink 10 figures 20, 21 5, 12 figure?10 400 bga heat sink 9 table 5. 3.3v output derating curve v in (v) power loss curve air flow (lfm) heat sink ja (c/w) figures 22, 23 5, 12 figure?13 0 none 14.5 figures 22, 23 5, 12 figure?13 200 none 12 figures 22, 23 5, 12 figure?13 400 none 11 figures 24, 25 5, 12 figure?13 0 bga heat sink 13.5 figures 24, 25 5, 12 figure?13 200 bga heat sink 10 figures 24, 25 5, 12 figure?13 400 bga heat sink 9 LTM4643 4643fb for more information www.linear.com/LTM4643
23 applications information v out (v) c in (ceramic) (f) c out1 (f) c ff (pf) v in (v) droop (mv) p-p deriv a tion (mv) recovery time (s) load step (a) load step slew rate (a/s) r fb (k) ceramic only 1 10 47 100 5, 12 1 59 40 2a to 3a 0 90.9 1.2 10 47 100 5, 12 1 59 40 2a to 3a 0 60.4 1.5 10 47 100 5, 12 1 66 40 2a to 3a 0 40.2 1.8 10 47 100 5, 12 1 75 40 2a to 3a 0 30.1 2.5 10 47 100 5, 12 2 108 50 2a to 3a 0 19.1 3.3 10 47 100 5, 12 3 111 60 2a to 3a 0 13.3 poscap 1 10 100 5, 12 1 89 40 2a to 3a 0 90.9 1.2 10 100 5, 12 1 94 40 2a to 3a 0 60.4 1.5 10 100 5, 12 1 108 40 2a to 3a 0 40.2 1.8 10 100 5, 12 1 120 40 2a to 3a 0 30.1 2.5 10 100 5, 12 2 144 50 2a to 3a 0 19.1 3.3 10 100 5, 12 3 161 60 2a to 3a 0 13.3 table 6 c in part number value c out1 (ceramic) part number value c out1 (poscap) part number value murata grm21br61e106ka73l 10f, 25v, 0805, x5r murata grm21br60j476me15 47f, 6.3v, 0805, x5r sanyo 4tpe100mzb 4v 100f taiyo yuden tmk212bbj106kg-t 10f, 25v, 0805, x5r taiyo yuden jmk212bj476mg-t 47f, 6.3v, 0805, x5r murata grm31cr61c226me15l 22f, 25v, 1206, x5r taiyo yuden tmk316bbj226ml-t 22f, 25v, 1206, x5r LTM4643 4643fb for more information www.linear.com/LTM4643
24 applications information safety considerations the LTM4643 modules do not provide galvanic isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. the device does support thermal shutdown and overcurrent protection. layout checklist/example the high integration of LTM4643 makes the pcb board layout very simple and easy. however, to optimize its electri - cal and thermal performance, some layout considerations are still necessar y . ? use large pcb copper areas for high current paths, including v in1 to v in4 , gnd, v out1 to v out4 . it helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output capaci - tors next to the v in , gnd and v out pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the unit. ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put via directly on the pad, unless they are capped or plated over. ? use a separated sgnd ground copper area for com - ponents connected to signal pins. connect the sgnd to gnd underneath the unit. ? for parallel modules, tie the v out , v fb , and comp pins together. use an internal layer to closely connect these pins together. the track/ss pin can be tied a common capacitor for regulator soft-start. ? bring out test points on the signal pins for monitoring. figure?28 gives a good example of the recommended layout. figure?28. recommended pcb layout LTM4643 4643fb for more information www.linear.com/LTM4643
25 typical applications figure?29. 4v to 20v input, quad 1.0v, 1.5v, 2.5v and 3.3v output with ratiometric tracking 4643 f29 v in1 svin1 run1 intv cc1 mode1 v in2 svin2 run2 intv cc2 mode2 v in3 svin3 run3 intv cc3 mode3 v in4 svin4 run4 intv cc4 mode4 sgnd LTM4643 clkin 10f 4 25v 1206 clkout temp gnd v out1 fb1 comp1 track/ss1 pgood1 v out2 fb2 comp2 track/ss2 pgood2 v out3 fb3 comp3 track/ss3 pgood3 v out4 fb4 comp4 track/ss4 pgood4 47f 6.3v 0805 3.3v/3a 4v to 20v 13.3k 0.1f 47f 4v 0805 2.5v/3a 19.1k 60.4k 13.3k 47f 4v 0805 1.5v/3a 40.2k 47f 4v 0805 1v/3a 90.9k 60.4k 13.3k 60.4k 13.3k figure?30. 2.375v to 5v input, quad 1v, 1.2v, 1.5v, 1.8v output 4643 f30 v in1 svin1 run1 intv cc1 mode1 v in2 svin2 run2 intv cc2 mode2 v in3 svin3 run3 intv cc3 mode3 v in4 svin4 run4 intv cc4 mode4 sgnd LTM4643 clkin 10f 4 6.3v 1206 clkout temp gnd v out1 fb1 comp1 track/ss1 pgood1 v out2 fb2 comp2 track/ss2 pgood2 v out3 fb3 comp3 track/ss3 pgood3 v out4 fb4 comp4 track/ss4 pgood4 47f 4v 0805 1.8v/3a 2.375v to 5v 1f 6.3v 5v bias 30.1k 0.1f 0.1f 0.1f 0.1f 47f 4v 0805 1.5v/3a 40.2k 47f 4v 0805 1.2v/3a 60.4k 47f 4v 0805 1v/3a 90.9k LTM4643 4643fb for more information www.linear.com/LTM4643
26 figure?31. 4v to 20v input, 4-phase, 1.2v at 12a design with temperature monitoring typical applications 4643 f31 v in1 svin1 run1 intv cc1 mode1 v in2 svin2 run2 intv cc2 mode2 v in3 svin3 run3 intv cc3 mode3 v in4 svin4 run4 intv cc4 mode4 sgnd LTM4643 clkin 22f 2 25v 1206 clkout temp gnd v out1 fb1 comp1 track/ss1 pgood1 v out2 fb2 comp2 track/ss2 pgood2 v out3 fb3 comp3 track/ss3 pgood3 v out4 fb4 comp4 track/ss4 pgood4 47f 3 4v 0805 1.2v/12a v in 4v to 20v 15.1k 0.1f r t v in a/d r t = v in ? 0.6v 100a LTM4643 4643fb for more information www.linear.com/LTM4643
27 typical applications figure?32. 12v and 5v two separate input rails, 1.2v at 6a and 3.3v at 6a output 4643 f32 v in1 svin1 run1 intv cc1 mode1 v in2 svin2 run2 intv cc2 mode2 v in3 svin3 run3 intv cc3 mode3 v in4 svin4 run4 intv cc4 mode4 sgnd LTM4643 clkin 22f 2 16v 1206 clkout temp gnd v out1 fb1 comp1 track/ss1 pgood1 v out2 fb2 comp2 track/ss2 pgood2 v out3 fb3 comp3 track/ss3 pgood3 v out4 fb4 comp4 track/ss4 pgood4 47f 2 4v 0805 1.2v/6a 5v 22f 2 16v 1206 12v 30.2k 47f 2 6.3v 0805 3.3v/6a 0.1f 6.65k 0.1f LTM4643 4643fb for more information www.linear.com/LTM4643
28 LTM4643 component lga and bga pinout package description package row and column labeling may vary among module products. review each package layout carefully. pin name pin name pin name pin name pin name pin name a1 v out1 b1 gnd c1 v out2 d1 v out2 e1 gnd f1 v out3 a2 v out1 b2 gnd c2 pgood2 d2 v out2 e2 gnd f2 pgood3 a3 v out1 b3 v in1 c3 pgood1 d3 gnd e3 v in2 f3 temp a4 gnd b4 v in1 c4 intv cc1 d4 gnd e4 v in2 f4 intv cc2 a5 gnd b5 sv in1 c5 gnd d5 gnd e5 sv in2 f5 gnd a6 track/ss1 b6 mode1 c6 run1 d6 track/ss2 e6 mode2 f6 run2 a7 fb1 b7 comp1 c7 clkin d7 fb2 e7 comp2 f7 sgnd pin name pin name pin name pin name pin name g1 v out3 h1 gnd j1 v out4 k1 v out4 l1 gnd g2 v out3 h2 gnd j2 pgood4 k2 v out4 l2 gnd g3 gnd h3 v in3 j3 clkout k3 gnd l3 v in4 g4 gnd h4 v in3 j4 intv cc3 k4 gnd l4 v in4 g5 gnd h5 sv in3 j5 gnd k5 intv cc4 l5 sv in4 g6 track/ss3 h6 mode3 j6 run3 k6 track/ss4 l6 mode4 g7 fb3 h7 comp3 j7 fb4 k7 run4 l7 comp4 LTM4643 4643fb for more information www.linear.com/LTM4643
29 package description please refer to http://www.linear.com/product/LTM4643#packaging for the most recent package drawings. lga package 77-lead (15.00mm 9.00mm 1.82mm) (reference ltc dwg # 05-08-1508 rev ?) package top view 4 pin ?a1? corner y x aaa z aaa z lga package 77-lead (15.00mm 9.00mm 1.82mm) (reference ltc dwg# 05-08-1508 rev ?) d e lga 77 0715 rev ? tray pin 1 bevel package in tray loading orientation component pin ?a1? ltmxxxxxx module detail a package bottom view 3 see notes a b c d e f g h j k l pin 1 e b f g 7 6 5 4 3 2 1 suggested pcb layout top view 0.000 2.540 3.810 5.080 6.350 1.270 3.810 2.540 1.270 5.080 6.350 3.810 2.540 1.270 3.810 2.540 1.270 0.3175 0.3175 0.000 0.630 0.025 ? 77x 7 see notes detail b detail b substrate mold cap // bbb z z a symbol a b d e e f g h1 h2 aaa bbb eee min 1.72 0.60 0.27 1.45 nom 1.82 0.63 15.00 9.00 1.27 12.70 7.62 0.32 1.50 max 1.92 0.66 0.37 1.55 0.15 0.10 0.15 notes dimensions total number of lga pads: 77 h2 h1 0.630 0.025 ? 77x s yx z? eee detail a notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 5. primary datum -z- is seating plane 6. pad finish: au 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature 7 package row and column labeling may vary among module products. review each package layout carefully ! LTM4643 4643fb for more information www.linear.com/LTM4643
30 package description please refer to http://www.linear.com/product/LTM4643#packaging for the most recent package drawings. package top view 4 pin ?a1? corner y x aaa z aaa z bga package 77-lead (15.00mm 9.00mm 2.42mm) (reference ltc dwg# 05-08-1559 rev ?) notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 6. solder ball composition can be 96.5% sn/3.0% ag/0.5% cu or sn pb eutectic 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature detail a ?b (77 places) detail b substrate a a1 b1 ccc z detail b package side view mold cap z m x yzddd m zeee symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 2.22 0.50 1.72 0.60 0.60 0.27 1.45 nom 2.42 0.60 1.82 0.75 0.63 15.00 9.00 1.27 12.70 7.62 0.32 1.50 max 2.62 0.70 1.92 0.90 0.66 0.37 1.55 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 77 a2 d e // bbb z z h2 h1 bga 77 0916 rev ? tray pin 1 bevel package in tray loading orientation component pin ?a1? ltmxxxxxx module detail a package bottom view 3 see notes a b c d e f g h j k l pin 1 e b f g 7 6 5 4 3 2 1 suggested pcb layout top view 0.000 2.540 3.810 5.080 6.350 1.270 3.810 2.540 1.270 5.080 6.350 3.810 2.540 1.270 3.810 2.540 1.270 0.3175 0.3175 0.000 0.630 0.025 ? 77x 7 package row and column labeling may vary among module products. review each package layout carefully ! 7 see notes LTM4643 4643fb for more information www.linear.com/LTM4643
31 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 03/17 added the bga package 1, 2, 28, 30 b 6/17 corrected output current from 4a to 3a on figure 4 corrected output voltage from 1.2v to 1.0v on title of figure 29 13 25 LTM4643 4643fb for more information www.linear.com/LTM4643
32 ? linear technology corporation 2016 lt 0617 rev b ? printed in usa www.linear.com/LTM4643 subject description module design and manufacturing resources design: ? selector guides ? demo boards and gerber files ? free simulation tools manufacturing: ? quick start guide ? pcb design, assembly and manufacturing guidelines ? package and board level reliability module regulator products search 1. sort table of products by parameters and download the result as a spread sheet. 2. search using the quick power sear ch parametric table. techclip videos quick videos detailing how to bench test electrical and thermal performance of module products. digital power system management linear technologys family of digital power supply management ics are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature eeprom for storing user configurations and fault logging. package photos related parts part number description comments ltm4644 higher power, quad quad 4a, pin compatible, 9mm 15mm 5.01mm bga ltm4623 single, ultrathin 3a, 6.25mm 6.25mm 1.8mm lga and 6.25mm 6.25mm 2.42mm bga ltm4622 dual, ultrathin dual 2.5a or single 5a, , 6.25mm 6.25mm 1.8mm lga and 6.25mm 6.25mm 2.42mm bga ltm4631 higher power, dual, ultrathin dual 10a or single 20a, , 16mm 16mm 1.91mm lga design resources LTM4643 4643fb for more information www.linear.com/LTM4643

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